This application relies for priority upon Korean Patent Application No. 2000-11087, filed on Mar. 6, 2000, the contents of which are herein incorporated by reference in their entirety.
1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly to dynamic random access memory (DRAM) devices having hierarchical arrangements with plural wordlines.
2. Discussion of Related Art
In a DRAM device, storage capacitors (or cell capacitors) retain the values of data, the charging/discharging path thereof being controlled by respective pass transistors (or cell transistors) disposed between a bit line and the capacitor. A gate electrode of the pass transistor is coupled to a wordline, and the switching of the transistor is dependent upon the voltage level on the wordline. Typically, to be effective, the voltage on the wordline is set at least higher than the power supply voltage of the DRAM, e.g., at 4 to 5V, so that the storage capacitor is sufficiently charged through the pass transistor. Such voltage level is obtained by boosting with a wordline driver. This is called xe2x80x9cself-boostingxe2x80x9d.
A memory cell array 10 of a DRAM, as shown in FIG. 1, is segmented into a plurality of memory cell blocks 16. Sub wordline drivers 14 are interposed between memory cell blocks 16 along column direction, and wordline drive signal generators 12 are disposed between the sub wordline drivers 14 along the row direction. The wordline drive signal generators 12 provide wordline drive signals PXiDB, PXiD, and PXiDP to corresponding sub wordline drivers 14. The wordline drive signal generators 12 are shared by the adjacent sub wordline drivers 14. Sense amplifiers 18 are arranged between the memory cell blocks 16 along the row direction.
FIG. 2 is a schematic circuit of a subwordline driver. Wordline WL is activated in response to decoding signal NWEi and the wordline drive signals PXiDB, PXiD, and PxiDP. The sub wordline driver is preferably constructed with NMOS transistors MN1, MN2, MN3, and MN6. NWEi is a decoded signal from row address signals in row decoder. The wordline drive signals PXiD, PXiDP, and PXiDB are provided from the wordline drive signal generator 12.
When NWEi is charged up to the boosted voltage level of 4xcx9c5 V (Vpp), node N1 goes to Vpp-Vt (Vt is a threshold voltage of NMOS transistor MN1) through the NMOS transistor MN1. And, when PXiDP is charged up to the boosted level Vpp together with NWEi, the voltage level at node N1 rises to 2Vpp-Vt, by means of xe2x80x98self-boostingxe2x80x99 through a junction capacitance in the NMOS transistor MN2. Therefore, the NMOS transistor MN2 is fully turned on, and thereby the voltage level on wordline WL is nearly identical to that of the wordline drive signal PXiDP. The row decoding signal NWEi and the wordline drive signal PXiDP have a self-boosting margin therebetween, which is a time interval between the boosted pulses of NWEi and PXiDP, for purposes of securing a time to pull the voltage levels up to the boosted level Vpp.
The wordline drive signal generators 12 are positioned between adjacent sub wordline drivers 14, and each generator is designed to have the same drive capability. The wordline drive signal generators 12xe2x80x2 arranged on a side of the memory cell array 10 is more capable in boosting PXiDP because they are not shared by adjacent sub wordline drivers 14 on each side. Thus, generators 12xe2x80x2 provide drives for one half of the wordlines in a memory cell block while the shared generators 12 provide drives for both halves of wordlines in adjacent memory cell blocks. As a result, an output signal PXiDPxe2x80x2 from the generators 12xe2x80x2 rises to the boosted level faster than an output signal PXiDP from the shared generators 12, causing the self-boosting margin to be reduced at the sub wordline drivers corresponding to the generators 12xe2x80x2. In general, the self-boosting margin over an entire chip is influenced by the generators 12xe2x80x2 to reduce the self-boosting margin of the entire chip.
Accordingly, it is an object of the present invention to provide a semiconductor memory device having stable wordline boosting operations.
It is another object of the invention to provide wordline drive signal generators capable of securing a stable wordline boosting operation.
A semiconductor memory device of the present invention accomplishes such objects. The memory device comprising: a memory cell array formed of cell blocks arranged in matrix of row and column; sub wordline drivers, interposed between the cell blocks arranged along column direction, each for driving a row of the cell block in response to a wordline drive signal; and wordline drive signal generators, disposed between the sub wordline drivers arranged along row direction, each for providing the wordline drive signal to the corresponding sub wordline driver. The wordline drive signal generators have variable drivability dependent on the position where they are placed on the memory cell array.
According to an aspect of the invention, the wordline drive signal generations are given different drive capabilities dependent upon the number of sub wordline drivers sharing the generator. Preferably, the drive signal generators driving a smaller number of sub wordline drivers are given less drive capability. Alternatively, the wordline drive signal generators arranged on sides of the memory cell array are given lower drivability than that of the wordline drive signal generators positioned between the sub wordline drivers.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.